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Preface
About This Guide
The ML50 x evaluation platforms enable designers to investigate and experiment with
features of Virtex?-5 FPGAs. This user guide describes the features and operation of the
ML505 (LXT), ML506 (SXT), and ML507 (FXT) Evaluation Platforms.
Guide Contents
This manual contains the following chapters:
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board components
factory settings for the clock chip on the ML50 x boards
Additional Documentation
The following documents are also available for download at
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Virtex-5 FPGA Family Overview
The features and product selection of the Virtex-5 FPGA family are outlined in this
overview.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 FPGA family.
Virtex-5 FPGA User Guide
This user guide includes chapters on:
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Clocking Resources
Clock Management Technology (CMT)
Phase-Locked Loops (PLLs)
Block RAM and FIFO memory
Configurable Logic Blocks (CLBs)
SelectIO? Resources
I/O Logic Resources
Advanced I/O Logic Resources
ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.2) May 16, 2011
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